Abishek Ramdas

I am a systems researcher and graduated recently from the Institute of Computing Platforms (Systems Group) at ETH Zurich with a doctoral degree. I am interested in emerging coherent interconnects and its impact on FPGA acceleration in a cloud setting. Prior to my doctoral studies, I worked at Qualcomm for 5 years as a post-silicon validation engineer with experience in Design for Test (DfT), CAD tool development and yield improvement. I love learning new things and enjoy having discussions and working in collaborative environments.

During my doctoral studies, I was part of the research team that built Enzian. I implemented an open, customizable, and performant cache coherence stack on the FPGA to demonstrate for the first time that an FPGA can be a peer to a server-grade CPU in the coherence protocol Gitlab. Through this process I picked up skills for reverse engineering coherence protocols from their traces, as well as modeling and verifying them. I used this coherence stack to research non-traditional acceleration models on FPGAs.